1. Field of the Invention
Broadly speaking, this invention relates to frequency synthesizers. More particularly, in a preferred embodiment, this invention relates to a frequency synthesizer of the indirect synthesis type, or a section thereof, which employs only one main phase-locked loop.
2. Discussion of the Prior Art
Frequency synthesizers fall into two general classes. In the first class, direct frequency synthesis is employed and new frequencies are derived from a single reference frequency by means of combinations of several additions, subtractions, multiplications and divisions of the reference frequency. This method is very complex and such a synthesizer is very expensive requiring a large number of passive and active elements.
The second class of synthesizers employs indirect frequency synthesis wherein new frequencies are derived from a single reference frequency by means of programmable phase-locked loops which contain whole number frequency dividers. If small steps in output frequency are necessary, then several phase-locked loops are employed, the output of one loop being divided and then added to or subtracted from the next. In other words, the output frequency of the synthesizer is divided down to a lower frequency for phase comparison with a reference frequency. A digital divider (with an integer divisor) provides an output frequency resolution which is directly related to the reference frequency. As higher resolution is needed, the reference frequency must be lowered. With a lower reference frequency, the short-term stability decreases and the phase-noise increases.
When short-term stability must be high and phase-noise low, a complex, multiple phase-lock loop system must be employed. Unfortunately, such multiple-loop, prior art synthesizers are expensive and complicated and it is very difficult to control spurious signals which may occur at many different frequencies, both close to and far away from the carrier frequency.
The problem, then, is to provide a frequency synthesizer which does not suffer from the aforementioned defects. This problem has been solved by the instant invention in which the digital divider in the phase-locked loop, is effectively made to divide in fractional steps so that a much higher reference frequency may be employed than that used in prior art systems. This permits the use of only one main phase-locked loop, in the aforementioned synthesizer or section thereof, thus holding generation of spurious signals to a minimum. A secondary phase-locked loop, used for the fractional dividing, does produce some close-to-the-carrier spurious signals, but if unacceptable this is effectively reduced by means of a tunable frequency discriminator, or a sideband reduction ramp generator or a combination of both.
U.S. Pat. No. 3,605,025 which issued on Sept. 14, 1971 to A. J. Lincoln discloses a fractional divider bearing a superficial similarity to the fractional divider disclosed herein. However, the Lincoln divider is very complicated and includes a cascaded array of counting stages, the overflow from a previous counter being used to inhibit conduction of an input pulse to the next stage.
U.S. Pat. No. 3,721,904 which issued on Mar. 20, 1973 to L. A. Verhoeven also teaches a frequency divider with a variable divisor, but the divisor is restricted to whole number integers. See also U.S. Pat. Nos. 3,701,027; 3,464,018; 3,544,906 and 3,691,471 for general background.